1. Field of the Invention
The present invention relates to a semiconductor device comprising semiconductor chips and a wiring layer, and a method for fabricating the semiconductor device.
2. Description of the Prior Art
Recently, the tendency that electronic equipments have higher performance, and are lighter, thinner, shorter and more down-sized makes semiconductor devices higher integrated, more functional and more down-sized as seen typically in ASIC of LSI.
Conventionally, wafers which have been processed are back-polished, and then diced and cut into respective pellets (also called semiconductor chips or semiconductor elements). Then, die bonding, wire bonding, resin sealing, etc. are performed on the respective pellets, and semiconductor devices are fabricated. The wire bonding electrically connects the semiconductor chips to lead frames.
For high-speed signal processing, semiconductor chips are recently flip chip bonded by using bumps.
The flip chip bonding may be performed by a method of bare chip mounting for mounting semiconductor chips on a print substrate as they are. However, in this method, it is difficult to handle the semiconductor chips. In consideration of retaining reliability, packaged semiconductor chips with bumps are used.
Recently, as a method for fabricating semiconductor devices comprising packaged semiconductor chips with bumps a method in which wiring, external terminals (metal posts), resin seal and bumps are formed on the wafer level, and the wafer is cut into respective semiconductor chips, and the respective semiconductor chips are packaged into CSP (Chip Scale Package) (Chip Scale International 99SEMI 1999) is proposed.
The thus prepared CSP is also called wafer level CSP.
Such semiconductor fabrication is called here wafer level semiconductor fabrication.
A partial section of such semiconductor device is shown in FIG. 9. In FIG. 9, reference number 110 represents semiconductor chips (also called simply chips); reference number 115 represents an electrode (also called a terminal), reference number 120 represents an SiN passivation; reference number 125 represents a polyimide layer; a reference number 130 represents a wiring layer; reference number 131 represents a seed metal layer; reference number 132 represents an electrolytic plated copper layer; reference number 140 represents a resin seal layer (epoxy resin layer); reference number 150 represents a metal post; reference number 160 represents a barrier metal; and reference number 170 represents a solder ball.
In FIG. 9, the terminals 115 of the semiconductor chips 110 are connected to the wiring layer 130 formed on the surfaces of the semiconductor chips 110. The wiring layer 130 is connected to the external terminals (called also the metal posts) 150. The external terminals (metal posts) 150 are connected to the solder bumps 170 via the barrier metal layer 160. A print circuit board is to be soldered by the solder balls 170 as bumps. The form of such semiconductor device, in which the semiconductor chips are mounted on the print circuit board, is similar to the conventional flip chip bonding for mounting semiconductor chips on print substrates.
The seal layer 140 is provided, burying the metal posts 150.
In FIG. 9, the metal posts 150 structurally requires a diameter (100-200 xcexcm) or about ⅔xc3x97 a diameter of the solder balls 170, and has an about 100 xcexcm-height. The metal posts 150 are thick and have high rigidity.
Accordingly, when such semiconductor device mounted on a print circuit board is repeatedly subjected to temperature changes, thermal distortions take place due to thermal expansion coefficients difference (xcex94xcex1) between the respective semiconductor chips and the mounted print circuit board takes place, and cracks occur in the semiconductor chips 110 below the metal posts 150.
The resin seal layer 140 is provided only on a surfaces of the semiconductor chips 110 where the wiring layer 130 is formed, which permits warps to occur. Accordingly, problems of poor flatness of the solder balls 170 and low mounting yields occur.
In view of the above-described problems, the present invention was made, and an object of the present invention is to provide a semiconductor device which does not permit cracks and warps to occur in semiconductor chips mounted on a substrate even when subjected to temperature changes, and which has accordingly high yields, and a method for fabricating the semiconductor device.
The present invention is a semiconductor device comprising a semiconductor chip having electrodes; an insulation layer formed on a surface of the semiconductor chip where the electrodes of the semiconductor chip are formed; and a wiring layer formed on the insulation layer, the electrodes of the semiconductor chip and the wiring layer being connected to each other via connection members disposed in the insulation layer.
The present invention is the semiconductor device wherein the connection members include wire bumps disposed on the electrodes of the semiconductor chip.
The present invention is the semiconductor wherein the connection members further include cured conductive pastes formed on the wire bumps.
The present invention is the semiconductor device wherein the connection members include a metal layer formed on the electrodes of the semiconductor chip, and cured conductive pastes disposed on the metal layer.
The present invention is the semiconductor device comprising a solder resist layer having openings, for covering the wiring layer, solder balls disposed in the openings of the solder resist layer, connected to the wiring layer.
The present invention is the semiconductor device wherein an additional insulation layer is formed on a surface of the semiconductor chip, which is opposite to the surface where the electrodes are formed.
The present invention is a method for fabricating a semiconductor device comprising the steps of preparing a wafer including a plurality of semiconductor chips with electrodes formed on; forming connection members on the electrodes of the respective semiconductor chips; forming an insulation layer in a thickness to cover the connection members on the surfaces of the respective semiconductor chips where the electrodes of the semiconductor chips are formed; polishing the insulation layer to expose the connection members;
forming an electroless plated layer on the insulation layer; and forming, with the electroless plated layer as a feeder layer of electric current, an electrolytic plated layer on the electroless plated layer selectively only in regions for a wiring layer; etching off the electroless plated layer except regions of the electroless plated layer corresponding to the electrolytic plated layer to form the wiring layer including the electroless plated layer and the electrolytic plated layer; and severing the wafer into the respective semiconductor chips to fabricate the semiconductor device.
The present invention is the method for fabricating a semiconductor device further comprising the steps of forming a solder resist layer having openings on the wiring layer; and forming solder balls in the openings of the solder resist layer, connected to the wiring layer.
The present invention is the method for fabricating a semiconductor device wherein the connection members are formed by forming wire bumps on the electrodes of the semiconductor chips by wire bonding.
The present invention is the method for fabricating a semiconductor device wherein the connection members are formed by forming cured conductive pastes on the wire bumps.
The present invention is the method for fabricating a semiconductor device wherein the connection members are formed on the electrodes of the semiconductor chips by forming a metal layer by sputtering and forming cured conductive pastes on the metal layer.
The present invention is the method for fabricating a semiconductor device wherein in the step of forming an electrolytic plated layer, a resist pattern of a prescribed configuration is formed on the electroless plated layer, and the electrolytic plated layer is selectively formed with the resist pattern as a plating-resistant mask.
The present invention is the method for fabricating a semiconductor device wherein in the step of forming an wiring layer by etching, the resist pattern of a prescribed configuration on the electroless plated layer removed, and then the exposed electroless plated layer is removed by soft etching without damaging the wiring layer.
The present invention is the method for fabricating a semiconductor device wherein the step of polishing the insulation layer is followed by surface roughening processing for roughening the surface of the insulation layer.
The present invention is the method for fabricating a semiconductor device wherein in the step of forming a solder resist layer, a photosensitive solder resist is formed by screen printing, to cover the wiring layer, and prescribed regions of the photosensitive solder resist are exposed and developed to form the openings so as to expose the wiring layer.
The semiconductor device according to the present invention, owing to the above-described constitutions, does not have easily cracks in the semiconductor chips even when temperatures change.
Especially in the case where the connection members are wire bumps, the wiring formed on the insulation layer and the electrodes of the semiconductor chips are electrically connected to each other via the wire bumps formed on the electrodes of the chips. The wire bumps are formed of Au wires or others, which are soft and ductile, and accordingly can be formed thin and high. Even when the semiconductor device is repeatedly subjected to thermal stresses, the wire bumps themselves are deformed to mitigate the stresses to hinder the occurrence of cracks in the semiconductor chips.
In the conventional semiconductor device, whose metal posts are hard and thick, cannot deform themselves and accordingly has relatively low strength. Cracks occur in the surface of the semiconductor chips, the connection portions of the solder balls, etc.
According to the present invention, in the case where the connection members are formed of the wire bumps formed on the electrodes of the semiconductor chips and the cured conductive pastes formed on the wire bumps, the insulation layer forming step can be easy. Besides, the reliability of the connection at the time when the semiconductor device is repeatedly subjected to thermal stresses can be higher.
That is, the cured conductive pastes can be formed on the wire bumps to be high and have a point to tops of the pastes. Accordingly, the connection members can be passed, without being deformed, through the insulation layer, which is to be formed in the later step by laminating an epoxy-based material as the insulation layer.
In the case where the connecting members are formed of the metal layer formed on the electrodes of the semiconductor chips and the cured conductive pastes formed on the metal layer, the step of forming the connecting members can be processed in the unit of a wafer, and processing amount can be small.
The cured conductive pastes can have a thermal expansion coefficient which is relatively equal to that of the insulation layer, and has flexibility. Even when the cured conductive pastes are repeatedly subjected to thermal stresses, no cracks occur in the cured conductive pastes. The reliability can be accordingly high.
Because of the insulation layer formed on the surface of the semiconductor chips, which is opposite to the side of the semiconductor chips, where the electrodes are formed, warps do not easily occur, and high mounting yields can be provided.
Because of the solder resist layer covering the wiring, and the external terminals in the form of the solder balls, which are provided in the external terminal forming regions, the semiconductor device can be easily fabricated.
According to the method for fabricating the semiconductor device according to the present invention, the semiconductor device is fabricated to have the above-described constitutions, whereby even when the semiconductor device mounted on a substrate is repeatedly subjected to temperature changes, cracks do not easily occur in the semiconductor chips, and the connection portions cannot be easily broken. Furthermore, warps do not easily occur, and accordingly high mounting yields can be provided.